1. Field of the Invention
The present invention relates to a semiconductor device and a method for fabricating the same. More specifically, the present invention relates to a method for fabricating a self-aligned contact hole in a semiconductor device.
2. Description of the Related Art
As integration of semiconductor devices has increased, multilevel-interconnection has become an indispensable technology for manufacturing semiconductor devices. In multilevel-interconnection, a variety and/or plurality of miniaturized wiring patterns at different levels of the device generally overlap with each other on a plurality of dielectric layers. However, conventional photolithography technologies can sometimes fail to obtain sufficient accuracy for overlapping the variety of patterns with each other on a semiconductor substrate. Because of such limitations of conventional photolithography technologies, a short circuit between conductive layers can occur during the process of forming a contact.
In order to solve the aforementioned problem, a self-aligned contact technology for forming a contact hole using an etching selectivity and topology of dielectric layers (such as silicon [di]oxide and silicon nitride) has been developed, which is briefly described hereinafter.
First, an intermetal dielectric oxide layer is deposited on a semiconductor substrate where a gate structure has been formed in advance. Then, a photoresist pattern is formed on the intermetal dielectric oxide layer by a photolithography process. The gate structure comprises a gate oxide pattern, a gate electrode pattern, a hard-mask nitride pattern, and a nitride spacer on the sidewalls thereof. After the photoresist pattern is formed, a contact hole is formed by dry etching the intermetal dielectric oxide layer using the photoresist pattern as an etching mask, thus exposing the spacer nitride pattern and a portion of the substrate. Subsequently, the photoresist pattern is removed and the contact hole is filled with a conductive material, e.g., metals. Afterward, a portion of the conductive material formed on the intermetal dielectric oxide layer (outside the contact hole) is removed or planarized so that the self-aligned contact including a contact plug is completed.
However, in the above conventional method for forming a self-aligned contact hole, an area of the substrate exposed by the contact hole can decrease because polymers (potentially a relatively large quantity) may disturb the etching process for forming the contact hole. The polymers can occur when the spacer nitride pattern is exposed during the dry etching. Then, an etching rate of the intermetal dielectric oxide in a bottom of the contact hole becomes conspicuously decreased, compared to that of the intermetal dielectric oxide in a top of the contact hole. In case of over-etching the intermetal dielectric oxide (e.g., in order to obtain a sufficient etching rate in the bottom of the contact hole), the etching selectivity of the oxide (i.e., the intermetal dielectric oxide layer) to the nitride (i.e., the spacer nitride pattern) may decrease. In this case, the nitride as well as the oxide can be etched so that the gate electrode pattern can be damaged. In addition, increasing a thickness of the hard-mask nitride pattern for protecting the gate electrode pattern may result in increase of the aspect ratio of the contact hole.